Verification Engineer/Sr. Verification Engineer
Job description - Responsible for the verification of digital blocks & Verification of complex SOCs.
- Working on SOC level and IP level testbench and verification environment
- Creation of coverage driven verification plans, development of block and chip-level verification environments
- Should be able to Architect OVM environment for a medium level IP of 50K gates and should possess working knowledge of AHB, AXI or OCP bus protocols.
- Maintain existing OVM environment, Architect new ones, Mentor and train junior engineers on OVM methodologies.
Requirements- Expertise in verification environment definition and setup, IP level and system level directed and random verification
- Expertise in OOPs concepts, SV based verification environment development
- Experience in one/more of the following system bus interfaces like PCI_Express, USB, SATA, SDIO, MIPI and /or AMBA.
- Knowledge of scripting, SVA
- Knowledge of memory controllers, CPU architecture is a plus
- Knowledge of considerations for performance, power and cost optimization is desirable
- Looking for highly motivated individuals and ability to deal with ambiguity
- Good debugging and problem solving skills
- Ability to work in a team environment
- Ability to work with external technology companies for combined development of SOCs
Apply - Please forward your resume to careers@optimuslogic.in
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